1. Field of the Invention
The present invention relates to a comparator, and more particularly to a comparator which has a simple logic circuit compared to a conventional adder or subtracter.
2. Description of the Conventional Art
A comparator for judging an input in relation to another input is divided into two types, a sequential comparator and a bit comparator. FIG. 1 is a schematic block diagram which shows an example of the sequential comparator. As shown therein, the comparator obtains complements of addends B0-B3, respectively, by a complementer 1 and using adders 2a-2d sequentially adds bit by bit the complements to corresponding augends A0-A3 from a highest bit to a lowest bit of the augends A0-A3, thereby judging sizes of the two inputs A0-A3, B0-B3 in accordance with a fact whether a carry is generated in the last adder 2d.
That is, when the first comparison is made for the higest bits, the larger bit is outputted, but if the compared bit are identical, a next comparison is made with respect to the lower bit.
For example, when adding A and B each of which is 4 bits, if there is generated a carry by performing the addition of corresponding bits from lowest bit, the carry is transferred to upper bits. While, when judging the sizes of A and B, a complement of one of A and B is first obtained, and then the addition is carried out from the highest bit, thereby determining whether or not a carry is generated. That is, if the carry is generated in the highest bit, the face whether there is generated the carry in the lower bit does not have any affect, and if the highest bit is zero, no carry is generated regardless of an addition result of the lower bit. Other than that, the generation of the carry in the low-order bit affects a CMP result.
FIG. 2 is a schematic block diagram illustrating an example of the bit comparator. As shown therein, in accordance with inputted bits of two numbers each of bit comparing units 1a-1d compares the bits of the two numbers, thereby generating LT (less than), GT (greater than), EQ (equal) signals, and a random logic unit 2 combines signals outputted from each bit comparing unit 1a-1d and thus lastly judges sizes of the signals.
FIG. 3 is a circuit diagram illustrating an example of a high-speed bit comparator which has a similar type to FIG. 2. The high-speed bit comparator includes a complementing unit 1 which consists of inverters 10-14 for comparing inputs A, B each of which is 5 bits and outputs a complement B' of the input B; a NAND logic unit 2 and a NOR logic unit 3 which obtain NAND outputs and NOR outputs, respectively, of the input A and the complement B'; a comparing unit 4 consisting of MOS transistors (TP.sub.i. TN.sub.i) which are switched in accordance with output signals of the NAND and NOR logic units 2, 3 and sequentially comparing value sizes from the highest bit.
In the thusly configured comparator, if a highest bit A4 of the input A is greater than a highest bit B4 of the input B (A4=1, B4=0), an output Y4 of the NAND logic unit 2 becomes `0` and an output Z4 of the NOR logic unit 3 also becomes `0`.
Accordingly, the PMOS transistor TP(4.4) of the comparing unit 4 is turned on and NMOS transistor TN(4.4) is turned off, and a connecting point thereof becomes a level equivalent to a source voltage level VDD, thus a judging result CMP becomes `1`, meaning that the input A is greater than the input B.
On the contrary, if the input B is greater than the input A (A4=0, B4=1), the output Y4 of the NAND logic unit 2 becomes `1` and the output Z4 also becomes `1`. Therefore, the PMOS transistor TP(4.4) of the comparing unit 4 is turned off and the NMOS transistor TN(4.4) is turned off, so that the connecting point thereof the result CMP becomes `0` and thus it is determined that the input A is smaller than the input B.
While, when the inputs A and B are identical, the output Y4 of the NAND logic unit 2 becomes `1`, while the output Z4 of the NOR logic unit 3 becomes `0`.
Therefore, the PMOS transistor TP(4.4) and the NMOS transistor TM(4.4) are all turned off, thus no output with respect to the judging result CMP and at this time next lower bits are to be sequentially compared.
The result CMP can be expressed as an equation (1) which is a Boole's inequality. ##EQU1##
Wherein, Y4' is an inversion signal of Y4, and when CMP=1, it is determined that A&gt;B.
However, in the conventional art, if only the lowest bits of the two inputs are different, all the upper bits thereof have be compared and accordingly it takes a long time until a resultant value is outputted. Thus, a logic level to the sequential comparator decreases, but a switching time increases due to the use of a multiple input gate such as the random logic unit. Also, when there are large numbers of bits for the two inputs, the number of the PMOS and NMOS transistors which constitute the comparing unit is accordingly increased, thereby increasing the size of the comparator, which results in the reduction in an operational speed thereof.